[SystemSafety] multi-core validation for aerospace

[Ian Broster]

Hi Chris

This is something that Rapita Systems can support. Our focus is on the timing and cross-core interference aspects covered in CAST-32A.

https://www.rapitasystems.com/services/multicore-timing

There is also a brochure on the page that is more informative - look at the bottom of the page.

Ian



On 13/11/2018 16:10, Chris Hills wrote:
Hi All

I have a customer who is looking at a project that will be multi-core processors for aviation use.  They are going to have to validate the system and its software. They are trying to work out how they would gather sufficient evidence for this.

They are looking at different cores on the same device.  Different cores could potentially run different functions each, or could use something across all the cores. Design is up in the air just now, so they are looking for a general certification approach and what they  would need to achieve this and  any ways they  could do it using more automated methods where possible.

Does anyone have any pointers for them to get started?
This is a UK based project.

Regards
  Chris
Phaedrus Systems Ltd
96 Brambling B77 5PG
FREEphone 0808 1800 358    International +44 1827 259 546
Vat GB860621831  Co Reg #04120771
Http://www.phaedsys.com<http://www.phaedsys.com/>  chills at phaedsys.com<mailto:chills at phaedsys.com>





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--
Dr Ian Broster
General Manager, Rapita Systems Ltd
Mob: +44 7963 469 090. Skype: ianb1469
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